1. Field
Embodiments of the present invention generally relates to methods for forming ultra thin structures on a substrate, and more specifically, for using multiple cycles of polymer deposition of photoresist (PDP) and etching to form ultra thin structures on a substrate suitable for semiconductor device fabrication.
2. Description of the Related Art
Reliably producing sub-half micron and smaller features is one of the key technology challenges for next generation very large scale integration (VLSI) and ultra large-scale integration (ULSI) of semiconductor devices. However, as the limits of circuit technology are pushed, the shrinking dimensions of VLSI and ULSI interconnect technology have placed additional demands on processing capabilities. Reliable formation of gate structure on the substrate is important to VLSI and ULSI success and to the continued effort to increase circuit density and quality of individual substrates and die.
A patterned mask is commonly used in forming structures, such as contact structure, gate structure, shallow trench isolation (STI), lines and the like, on a substrate by etching process. The patterned mask is conventionally fabricated using a lithographic process to optically transfer a pattern having desired critical dimensions to a layer of photoresist. The photoresist layer is then developed to remove the undesired portions of the photoresist, thereby creating openings in the remaining photoresist through which underlying material is etched.
In order to enable fabrication of next generation, submicron structures having critical dimension of about 55 nm or less, optical resolution limitations of the conventional lithographic process must be overcome to reliably transfer critical dimensions during mask fabrication. Developing new lithographic tools and techniques pose significantly research investment and integration cost. As such, the inventors recognize the potential of extending available fabrication tools to sub 55 nm and smaller device dimensions as one solution for addressing this challenge.
Furthermore, as the geometry limits of the structures for forming semiconductor devices are pushed against technology limits, the lateral dimensions of features of integrated circuits formed on the substrate has shrunk to the point that tighter tolerances and precise process control are critical to successful fabrication. However, with shrinking geometries, precise critical dimension and etch profile control have become increasingly difficult. One problem found during plasma submicron 55 nm etching processes is control of the sidewall roughness of the etched structure, which may result in formation of anisotropic striation. As the dimensions of the features continue to diminish, sidewall striation and/or post-etch sidewall roughness occurrence in small critical dimension structures pose a significant challenge to structure profile integrity, which may ultimately deteriorate overall device performance.
Therefore, there is a need in the art for improved methods to fabricate ultra thin structures on a substrate.